Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof.
A semiconductor device, such as a power transistor, generally has a source area formed on a semiconductor substrate and a drain area formed below the source area so that a channel is formed in a vertical direction. The device (e.g., power transistor) has a structure including a gate electrode filled in a trench formed in the semiconductor substrate.
In general, if the thickness of an oxide layer formed on the gate electrode is too great, the thick oxide layer may negatively affect the performance of the semiconductor device (e.g., power transistor). The oxide layer may be grown during a heat treatment process for an ESD (Electrostatic Discharge) protective circuit and a dopant diffusion process so that the oxide layer has thickness of about 580±40 Å.
However, in general, the oxide layer formed on the gate electrode should have thickness of about 180±30 Å to have a positive effect upon performance of the device. When a thick oxide layer (e.g., 580±40 Å) is subsequently etched, defects may be generated due to over-etching.
For example, if the oxide layer has thickness of about 580 Å, the oxide layer must be removed by thickness of about 400 Å (e.g., by etching with a mixture of DIW [deionized water] and HF). At this time, a deviation of about ±40 Å may occur.
Thus, the oxide layer may be over-etched or under-etched, causing problems with the performance of the device.